Testing the operation of an integrated circuit and determining that it is operating as desired has become increasingly difficult as integrated circuit complexity has increased. Adequate testing frequently requires the testing of internal circuits that are not directly accessible from the device's terminals. One technique for testing internal circuits is known as boundary scan, defined as a standard by the Joint Test Action Group (JTAG). Boundary scan is especially useful for testing complex digital logic buried deep within complex integrated circuits such as microprocessors. Another testing method, known as built-in self test (BIST), is useful for faster, at-speed testing of circuits with large, regular structures such as integrated circuit memories. BIST uses a small controller circuit on the chip to carry out tests on command and to provide the results to an external agent. BIST enables faster testing of large on-chip memory structures at the expense of additional area and power costs for on-chip test logic. The architecture for memory BIST logic should enable the at-speed testing of the on-chip memories while making acceptable tradeoffs between power and chip area.
For example, many modern microprocessors include two or more CPU cores, each including a dedicated level 1 (L1) cache memory and a shared or dedicated level 2 (L2) cache memory. Since the L2 cache memory is large and regular, it is an excellent candidate for testing using the BIST method. Moreover to reduce test time and to enable optimal use of chip area for test purposes, the BIST logic can be distributed by separating the controller into a master BIST controller, which provides test instructions and data patterns, and several slave BIST controllers that execute the test on an adjacent portion of the L2 cache memory. The slave BIST controllers are customized for the corresponding circuits under test while the master BIST controller can service multiple slave BIST slave controllers.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.